Where to find documentation about the device tree pinctrl parameters?

I’m trying to add a new ethernet device to an existing stm32mp1 board, but i’m a bit lost in the device tree section.

What i found so far:

In the board.dts file, i could find the pins which connects to the ethernet phy:

&pinctrl {
        ethernet0_rgmii_pins: rgmii-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
                                 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
                                 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
                                 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
                                 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
                                 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
                                 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <2>;
                };

                pins2 {
                        pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <0>;
                };

                pins3 {
                        pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
                                 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
                                 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
                                 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
                                 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
                                 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
                        bias-disable;
                };
        };
};

&ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins>;
        pinctrl-names = "default";
        phy-mode = "rgmii";
        phy-handle = <&phy0>;
        st,eth_clk_sel = <1>;
        max-speed = <1000>;
        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "eth-ck", "syscfg-clk", "ethstp";
        clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, <&rcc ETHCK_K>, <&rcc SYSCFG>, <&rcc ETHSTP>;

        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                        ti,dp83867-rxctrl-strap-quirk;
                };
        };
};

For example in the pins1 section the following pins are connected:

pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
         <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
         <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
         <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
         <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
         <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
         <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */

But how and where is the order defined? How is it passed later to the phy device driver? What if i change the phy from rgmii to rmii? Then the number of pins reduce, but in what order do i have to place the pins?

Sadly i just can’t find any documentation to it, maybe someone can help me out here.

Thanks.

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Author: hberg539