From a hardware perspective, Servers have PCI memory management that assigns address translation across Global Memory on the board. 2 parts to this Q :
Is there a permanent partition available that functions with GTK compiled kernels, transparent to the PCI multiplexer (really a bus arbitrator) The IBM P8 architecture has 2 CPU to memory direct bus ports. Of course P8 has its own Linux seat compilers, not sure how Source code translates mem addressing in Tensor to a GPU that indexes flat mem map to DRAM on Server. I don’t want to malloc
or pin the DRAM.
I believe boundaries can be set up to prevent heap / stack ingress into a central DRAM area.. This is on a 512GB Server.
Is it possible to set each Xeon memory completely independent on an E5 2690 ; CPU I / CPU 2 each has independent 256GB address space. Thread allocation to RAM would be great , only how to also run from legacy Heap / Stack .. This is useful to avoid garbage collecting in the mem mapped area.
I am hardware design eng .. Is dev of non Mem leakage in Kernel / UniKernel avail ?
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Author: Rus Talis